Abstract
This thesis investigates the techniques to reduce the silicon area of CMOS current-steering digital-to-analog converters (DACs) without compromising the circuit linearity. Conventional high-resolution DACs have to pay a penalty of large-size transistors to get better matching characteristics, thereby increasing the fabrication cost. In this thesis, two methods are proposed to achieve low-cost and high-resolution current-steering DACs. A self-correction method is developed in the first work. To minimize the area, the transistor size of current source array is reduced deliberately. This shrink will corrupt the DAC linearity performance. With the assistance of a current comparator, a calibration DAC (CalDAC) and calibration logics, two calibration loops are employed to estimate the current mismatches. Since all calibration processes work in the digital domain, the overhead for analog circuit is minimized. In the meanwhile, the proposed methodology can be easily ported to other high-resolution current-steering DACs, especially for deep-submicron processes. We designed a 12-bit video DAC prototype to demonstrate the proposed scheme. Experiment results show the proposed method reduces the DNL and INL to 0.26 and 0.42 LSB, which guarantees 12-bit linearity. At 400-MS/s update rate, the spurious-free dynamic range is above 59 dB within a 30-MHz bandwidth, which corresponds to the signal bandwidth for HDTV applications. This prototype occupies only 0.18mm^2 die area including all calibration functions in a standard 90- nm CMOS technology. Besides the calibration, dynamic element matching (DEM) is another effective method to increase the spurious free dynamic range of DACs. The second work describes a new DEM method called Random Swapping Thermometer Coding (RSTC). The direction selected for a sequence of unit current sources will be randomly changed. Combining this method with the restricted jumping technique the low-frequency idle tones can be mitigated. This approach minimizes the number of switched elements and transient glitches as code changes, while achieving good spectrum purity as other DEM implementations. This method is applied to a 14-bit current-steering DAC with a 4+4+6 double-segmented structure. The first four bits (MSB) and the middle four bits (ULSB) are converted into thermometer codes and employ the proposed RSTC algorithm, which can relax the matching requirement on current cells. The test chip draws 70mW from the supplies with 20mA full-scale current, and occupies only 0.28 mm^2 active area in a standard 55-nm CMOS process. From measurement results of the test chip, it has been shown to display only 10-bit static linearity with INL around 16LSB. The dynamic performance obtained after applying RSTC algorithm is enhanced from 62dB to 79dB at low frequencies for a 100MHz sampling clock.