Abstract
IPs and memory cores are two key components in system-on-chip (SOC). The reuse of IP cores results in test integration challenges. In addition, the usage of mass heterogeneous memory cores in SOC also increases the cost of memory testing. These two issues make the test cost, especially that related to test integration, one of the major costs in SOC development. How to reduce the cost of logic core and memory testing becomes an important subject so far as SOC development is concerned. Although there have been plenty of research works on individual topics about SOC testing, few of them took into account the practical integration issues. The proposed Test Access Control System (TACS) allows easy test integration. Based on the IEEE P1500 Test Wrapper, a flexible test access mechanism (TAM) and the associated test controller are developed. In addition, an SOC test integration platform—SOC Test Aid Console, called STEAC—is also proposed to integrate SOC testing automatically. The proposed test architecture (TACS) and integration platform (STEAC) also solve the practical SOC test integration issues, including real problems found in test scheduling, test I/O reduction, timing of functional test, scan I/O sharing, etc. A test scheduling model is proposed based on our test architecture and test access mechanism (TAM), considering I/O resource constraints. Detailed scheduling further reduces the overall test time of the system chip. In addition, a test wrapper architecture is presented, which supports the coexistence of scan test and functional test. The test integration platform has been applied to an industrial SOC case. Based on the design experience and simulation results, our approach is simple and efficient—low test integration cost, short test time, and small area overhead. In addition, memory testing is becoming the dominant factor in testing a SOC, with the rapid growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SOC designs—BIST for RAM in Seconds, called BRAINS. BRAINS targets automatic test integration of multiple and heterogeneous memory cores in an SOC environment. The automatic test grouping ptimizes the overhead in test time, performance, power consumption, etc. With a configurable and extensible architecture, the proposed framework facilitates easy memory test integration for core providers as well as system integrators. With the proposed SOC test integration platform (STEAC) and BIST generation framework (BRAINS), the core test reuse and heterogeneous memory testing in SOC can be solved. Both help reducing the test integration cost. In addition, the integration of logic core testing and memory core testing is presented. A centralized test controller can handle the testing of logic cores and memory cores. This further reduces the test cost in SOC test integration.