Abstract
Under 90nm technologies, variability, such as PVT variation and multiple design modes/corners, have become one of leading causes for chip failures. The delay uncertainty raised by PVT variation may cause a design to fail its’ timing specification. In addition, it has becomes tremendously difficult to create a single layout that satisfies numerous constraints imposed by the multiple modes of operations. In this thesis, we propose three mechanisms for reliability and timing optimization considering variability. We first propose an error-detecting architecture (TED) to detect and correct timing errors caused by PVT variation. This TED architecture can tolerate delay variation and enhance timing reliability without the short path problem in previous works. Second, the traditionally strategy of optimizing a circuit for the rarely activated worst-cases conditions could lead to inefficient resource use. We propose a re-synthesis method based on variable-latency design style to improve design performance. Finally, considering multiple design modes, building a single clock network to satisfy all constraints in each mode is difficult. We insert adjustable delay buffers (ADB) whose delay can be tuned in each mode into clock tree to simultaneously satisfy multiple clock skew constraints. We propose a linear-time optimal algorithm which assigns the values of ADBs so that the skew is optimal among all assignments. In addition, to obtain the accurate probability information of rare activation, we also propose an efficient approach to find the timing distribution of a circuit.