Abstract
As the technology and the application of the cloud computing are more and more mature and popular, data center not only is the core of the cloud computing but directly effects its performance. According to the suggestions from the major network manufactures, data center networks are constructed based on the currently mainstream input-buffered switches interconnected to form fat-tree topology and enables the service provided by the backend servers. But in the fat-tree topology the required link bandwidth is increased exponentially as aggregation level raising. Furthermore, the speed of the network processor in the input-buffered switch must be increased. Therefore, the scale or the performance of the data center network will be limited. To handle the above challenges, a fat-tree topology can be treated as a Benes network in terms of topology equivalence. Benes networks, that are able to realize all input-output permutations, have been widely used to construct switch fabrics, and therefore we might view a fat-tree topology as a switch fabric. The unique property of the scalable load-balanced switch achieves 100% throughput by all internal decomposed switching nodes periodically running predefined connection patterns despite traffic distribution of external network. Applying the schedule of the load-balanced switch on the internal switching nodes in a fat-tree topology, we do not need any network processors, because all internal switching nodes switch cells are based on predefined connection patterns. Since the schedule of the load-balanced switch only requires one cycle permutations, we can reduce not only the required bandwidth but also the complexity of the switching network from the Benes network to the banyan network by the bit reversal permutation. To realize the fundamental switching device that can be used to construct an NP-free fat-tree topology, we propose several design solutions to meet the practical challenges, complete the Verilog modules of the linecards and the switch fabrics, and develop a 18-layered-PCB and programmable hardware platform. Integrating the programmable PCBs of the Verilog modules of the linecards and the switch fabric respectively into a standard AdvancedTCA chassis and connecting with two external Intel network processor development platforms, we finally complete a prototype of the load-balanced switch.