Abstract
In this thesis, a codec architecture of Hermitian codes which is able to target a low hardware complexity of implementation is presented. By exploiting the theory of Grobner bases for modules, we develop a serial-in-serial-out hardware architecture, similar to a classical cyclic encoder, for the systematic encoding scheme of Hermitian codes. By deriving the upper bounds of the numbers of memory elements and constant multipliers in the proposed architecture, we show that the complexity of our architecture is much less than that of the brute-force systematic encoding by matrix multiplication. Similar to the decoding of Reed-Solomon codes or BCH codes, we divide the procedure for the decoding of Hermitian codes into four steps: generating known syndromes from a received word, producing an error-locator polynomial, searching for the potential error points (positions) and evaluating the error values. Based on the regular algebraic properties of the (x,y)-coordinates of all finite rational points on the Hermitian curve, we extend the use of Horner's rule and the mechanism of Chien search in the decoding of Reed-Solomon codes to render up efficient architectures for syndrome generation and error location search. By adopting Liu-Lu algorithm, we present a hardware architecture for finding the error-locator polynomial with least pole order at Q, where Q is the rational point at infinity of the Hermitian curve, via one-dimensional systolic arrays. With the extended syndrome matrix M and the r-shift properties, where r is the smallest nonzero nongap of the Hermitian curve, only r columns will be examined simultaneously in Liu-Lu algorithm. Thus only a series of t+(g-1)/2+1 processing elements, called PE cells, g delay units, called D cells, and r operation elements, called OE cells, are needed in our architecture, where g is the genus of the Hermitian curve and t is the designed error correcting capability of the Hermitian code . Finally, we modify the Hansen's algorithm to fit our case that only one error-locator polynomial is given and propose an efficient architecture via one-dimensional systolic arrays for the determination of the error values.