Abstract
由於VLSI技術不斷的提升,使得可以容納在單一晶片上的電路越來越多,造 成在晶片的測試工作上,不論是測試樣型的尋找,或是找出品質不良晶片的 困難度皆明顯的增加.尤其是偵錯模擬,針對單一測試樣型而言,它的時間 複雜度是隨著電路大小的二次方成長,因此,加速偵錯模擬的研究越來越顯 得重要;另一方面,也因為VLSI技術不斷的提升使得硬體價格相對地降低, 使得利用平行運算方法來加速偵錯模擬的研究逐漸受到重視.傳統的平行 處理方式是使用電路切割法將被模擬電路切成數個部份,然後將每部份電 路分配到每個處理器上,每個處理器負責一部份的電路模擬,此一方式的缺 點是,由於信號間的依賴關係使得信號的傳遞可能必須透過處理器之間的 傳輸來達成.當使用的處理器數目很多的時候,傳輸的負擔會相當重而使得 整個系統的速度瓶頸在傳輸上面.此外傳統方式的系統速度也被電路的平 行度所限制住.在論文中,我們提出了用二維細胞式自動機架構來加速邏輯 與偵錯模擬的方法,為了實現上述的平行架構,我們提出一具有導管式執行 能力的超大型積體電路架構,此一晶片架構具有二維式擴充能力,可依被模 擬電路大小來組成不同大小的系統.以往的分散式偵錯模擬大都採用樣型 切割或錯誤切割法,我們將討論採用電路切割的分散式偵錯模擬的可行性, 此外我們也提出分散式平行樣型平行錯誤傳遞法偵錯模擬,並且討論結合 樣型切割與錯誤切割的分散式偵錯模擬.本文分五章,第一章緒論,第二章 參考文獻回顧,第三章快速處理邏輯與偵錯模擬的細胞式自動機,第四章細 胞式自動機之超大型積體電路架構與電路設計,第五章分散式邏輯與偵錯 模擬,第六章結論. Parallel processing and distributed computing approaches provide faster simulation environment than algorithmic improvement. Traditional parallel logic and fault simulation applies circuit partitioning approach to divide the circuit under simulation into different processors such that each processor simulates a small portion of the original circuit. Concurrent simulation and smaller problem instance are the benefits. However, limited and unpredictable circuit parallelism and increasing processor communication overhead with respect to the number of processors reduce simulation speed-up. In this dissertation, we propose a novel SIMD parallel architecture, i.e., a unilateral 2-D cellular automata (CA) model, to embed the simulated circuit. Cooperating CA cells preserve the circuit structure and perform pipelined logic and fault simulation. Different from the traditional parallel processing approach by circuit partitioning, the maximum potential parallelism for our parallel architecture is the gate count of the circuit, and is not constrained by the circuit parallelism. With the encouraging results, we propose a CA chip with a pipeline control unit. Detailed implementation process is presented and discussed in this thesis. The CA chip architecture is scalable in both dimensions, which is standard-cell based. It produces one output in every six CA clock cycles after the pipeline has been filled in the initial simulation stage, which corresponds to the results of the software simulator. Distributed fault simulation by fault set partitioning or test set partitioning is general and popular. We investigate the feasibility of distributed fault simulation by circuit partitioning. We present a distributed PPPFP simulation to promote the server utilization. We also present another distributed simulation by combining test partitioning and fault partitioning.