Abstract
Power gating is one of the most effective ways to reduce leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area for power gating by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current flowing through sleep transistors. In this thesis, we propose two sleep transistor sizing methodologies for leakage power minimization. First, we present an O(n lg n)-time algorithm for efficiently estimating a tight upper bound of the voltage drop across sleep transistors in DSTN structure. Our algorithm takes the correlation between discharge current of different logic clusters into consideration, which avoids over-pessimistic voltage drop estimation. Secondly, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep transistor networks from a temporal viewpoint. Based on this relationship, we propose an algorithm to reduce the total sizes of sleep transistors in DSTN designs. In our sizing method, the effect of decoupling capacitances is also taken into account since decaps are commonly inserted in a power gating design to reduce the IR drop noise. Also, the convergence of our sizing algorithm is guaranteed through the theorem we proposed.