Abstract
The continuous scaling down of gate silicon dioxide thickness in metal-oxide-semiconductor devices achieves continued improvement in integrated circuit performance. However, the accompanying high leakage current of ultrathin silicon oxide is a significant problem for IC application. A high-k gate dielectric with a large physical thickness and an identical equivalent oxide thickness has recently been proposed to solve this leakage issue. Among various high-k gate dielectrics, Hf-based gate dielectrics have received much attention. Properties with better reliability can be obtained by higher nitrogen pile-up at the dielectric/Si interfaces. More nitrogen incorporated into gate dielectric bulk can result in more significant charge trapping. A greater amount of nitrogen incorporated into the dielectric/Si interface can result in less strain near the interface and a smaller defect generation rate. In addition, the XPS results show that the O 1s peak for the Si(111)-substrate sample is lower than that for the Si(100)-substrate sample while the N 1s peak is higher for the former than for the latter. Crystalline retardation was found to be significant for the HfOxNy film deposited onto the Si(111)-substrate as characterized by XRD. According to the investigations upon SILC and Tbd, the reliability characteristics of high-k gate dielectrics deposited on a Si(111)-substrate are better than those deposited on a Si(100)-substrate. The current-conduction mechanism of the HfOxNy film at low-temperature range and high-field, the low-electrical field and high-temperature, the high-electrical field and high-temperature is dominated by tunneling, Schottky emission and Frenkel-Poole emission, respectively. The trap energy level involved in FP conduction was estimated. A low defect (denuded zone) at Si surface was formed by a high-temperature annealing. Our results reveal that HfOxNy demonstrates a significant improvement on the electrical properties of MOS devices owing to its low amount of the [Oi] and the crystal-originated particles defects and better surface quality at the IL/Si interface. Moreover, after plasma etching, a chemical dry clean treatment was applied to achieve a smoother surface and to reduce carbon and fluorine residues contamination. Based on the investigations upon leakage current, stress induced leakage current, time to breakdown, interface roughness, and ideality factor, chemical dry clean treatment has shown to be an effective process to improve electrical and reliability characteristics of high-k MOS devices.