Abstract
In this study, a performance analysis methodology is first proposed for BiNOR flash memory. The BiNOR flash memory means that the bi-directional Fowler-Nordheim tunneling effect is adopted for programming/erasing operations in a NOR-type array configuration. With the bi-directional channel Fowler-Nordheim tunneling operations, power consumption can be tremendously reduced, and the cell reliability can be greatly enhanced. With the NOR-type array configuration, fast random access can be achieved. Through device modeling, the impact of the device dimensions and the process parameters on the device characteristics can be comprehensively investigated. Based on the theoretical deductions, a ramped pulse programming method is proposed to achieve the linear programming characteristics. The electric field during operation can be effectively reduced to improve the cell reliability. The self-convergent behavior helps controlling the programmed threshold voltage accurately. Experimental results also demonstrate a tightened threshold voltage distribution. Several schemes based on the ramped pulse programming are presented to achieve multi-level operations. Wherein, a ramped pulse programming method with different bit line voltages is the most promising candidate for multi-level charge storage with minimum circuit overhead. Besides, a graded gate oxide technology combined with a lightly doped source line structure is proposed for eliminating the programming disturbance without degrading the performance. Finally, a triple well isolation is adopted for applying a negative source voltage to reduce the erasing voltage. The peripheral high voltage circuits can thus be simplified and the overall chip area is reduced.