Abstract
In deep sub-micron VLSI technologies, the interconnect delay has become a dominant factor affecting performance of ICs. Wirelength reduction is the most fundamental objective in the P&R stage. Compared with traditional Manhattan architecture, X-architecture and Y-architecture—the new architectures—, provide more available routing directions correspond to different metal layers for chip interconnection to reduce wire length. However, these cause a lot of unexpected via count as a result of multiple metal layers being crossed in order to achieve specialized routing direction. In this paper, we propose a two-stage clock routing algorithm for λ-geometry plane. In global routing stage, we present a general zero skew clock tree construction algorithm with minimum wirelength under any kinds of routing architecture (λ-ZST). In detailed routing stage, two effective and efficient approaches (NVM and BVM) are used for decreasing the potential via count. Compared with the Manhattan architecture, our λ-geometry clock router achieves, on average, a 7.57% wirelength reduction in Y-architecture and 9.68% in X-architecture. In our experimental result, using NVM and BVM shows an average reduction in the via count of 17% in Y-architecture and 37% in X architecture respectively.