Abstract
The goal of this thesis is to use self-aligned p-well and n-source ion implantation with tilting an angle to fabricate a short channel 4H-SiC double implant MOSFET. Also with a self-aligned ohmic contact process, the device cell pitch can be shrunk and hence the specific on resistance is expected to reduce significantly. In this experiment, we have demonstrated D-mode DMOSFETs with the proposed process and the best RON,SP is 57.95 mΩ*cm2, extracted when Vg = 20 V and Vd = 1 V on a device with a smaller active area of 31482 um2, a longer effective channel width of 5004 um and a JFET length of 4 μm. The best breakdown voltage measured in this work is only 700 V on a sample with a epi-layer thickness of 30 μm. And the possible explanation is the incomplete p-well ion implantation activation at 1650oC anneal, which causes lateral punch-through at high reverse biases.