Abstract
CMOS image sensor has been widely used in various applications, such as video camera, digital camera, mobile phone, PDA, and laptop. The demand of CMOS image sensor is expected to rise rapidly in the next few years. As high-level integrated chips, SoC (system-on-chip), CMOS image sensor might replace CCD to become the mainstream product as the first semiconductor imaging choice. The conventional logarithmic-mode CMOS image sensor demonstrates wide dynamic range comparing to the linear-mode CMOS image sensor. But its low output voltage swing and large FPN (Fixed Pattern Noise) make it less attractive. A novel logarithmic response CMOS image sensor for 0.25μm CMOS technology is proposed. The new cell has a much higher output voltage swing than a conventional structure, making it more compatible with the A/D converter. In addition, to reduce the FPN in logarithmic mode CMOS APS (Active Pixel Sensor), a new cell with in-pixel CDS (Correlated Double Sampling) control, is proposed. The FPN (Fixed Pattern Noise) of this new logarithmic-mode image sensor can be greatly reduced from 54mV to 10mV. Furthermore, the output signal variation of the log-mode CMOS APS combined with lateral PNP and an in-pixel CDS control transistor due to FPN can be greatly reduced from 27% of Vsat RMS (total signal voltage range) to 2.46% of Vsat RMS.