Abstract
Power MOSFETs in Silicon Carbide (SiC) have the potential of high breakdown, high temperature operation and low specific on-resistance due to its high avalanche breakdown field and large thermal conductivity. In this thesis, we demonstrate a high-voltage lateral 4H-SiC MOSFET on a semi-insulating substrate with two-zone and field plate structures. Two RESURF zones with lower dose in zone1 close to the gate and higher dose in zone2 close to the drain can reduce the electric field near the gate oxide without increasing the specific on-resistance. Field plates are also employed at the gate and the drain to enhance the breakdown voltage. Semi-insulating substrates are used to avoid substrate assisted depletion effect and the vertical breakdown. Different from our previous work, we successfully suppress the surface roughening by using a graphite cap during high-temperature activation. In addition, gate oxide annealed in NO ambient is used to passivate the interfaces at SiO2/4H-SiC after thermal oxidation. From measurements, the best blocking voltage of 3500V with a specific on-resistance of 435 mΩ-cm2 is obtained on a device with Lch=5μm and Ld=80μm. Devices are fabricated with circular and linear gate, and the linear ones show worse trapping effects and larger leakage current. This might attribute to dry-etch induced defects on the sidewalls of the isolation trench.