Abstract
The BCD process technology combines the BJT, CMOS, and DMOS transistors into the same chip and integrates their advantages. In this thesis, we use the simulation software of process and electricity to analyze the influence of different layout on current gain and electricity of BJT in 0.25um BCD process, and further design the BJT device with high current gain. By having the chance of actual tapeout, some of the BJT devices from simulation are chosen as the BJT structures to be tapeouted. The results of actual device structures measurement and electrical analysis show that the BJT device structures which can provide higher current gain and improve the characteristics of amplifying are actually carried out. Furthermore, The simulation software are also utilized to design N channel JFET which have good turn on characteristics, and via actual tapeout, we have successfully integrated N channel JFET into the 0.25um BCD process, which provides IC designer more choices of devices. It is also beneficial to utilize the merits of JFET to improve the performance of the whole circuit.