Abstract
In this work we try to extend the maximum operating frequency achievable by all-digital delay-locked loop (DLL) based frequency multiplication circuit to support a high-speed range of 1GHz to 4GHz, to be used by our in-house radar system on chip (SoC). This goal is achieved by an innovative architecture in which an 8 phases of 1GHz clock signals pre-generated using techniques proposed in [12] and [13] are combined to form the waveform of the final target clock signal. Post-layout simulation result shows that the frequency error of the generated 4GHz clock signal is below 0.01% with a 7.48ps RMS-jitter, and the active area and the power consumption is 0.104mm2 and 12.67mW respectively.