Abstract
This thesis describes a 100MHz, 8-bit resolution CMOS fully differential sample-and-hold circuit under 1.8V operation voltage. The circuit is composed of a high-speed operational amplifier, capacitors, MOS transistor switches, and a high voltage generator. The fully differential folded cascode structure is used in the design of high-speed operational amplifier. A DC gain of 55.9dB, and an unity gain frequency of 515MHz with 2p load capacitors, are obtained. The sample-and-hold circuit uses the correlated-double-sampling structure to reduce the offset voltage, gain error, and noises. A high voltage generator circuit is used to boost the clock to obtain better linearity. This circuit achieves 8-bit resolution when operating at 100MHz clock rate with 1 Vpp input signal, and the input signal bandwidth is up to 25MHz. The total power consumption is 34mW.