Abstract
A 10-bit 200-MS/s pipelined analog-to-digital converter (ADC) using virtual ground reference buffer and foreground calibration technique in TSMC 0.18μm standard CMOS process technology is presented. The simulated ADC performances achieve -85 dB of Noise Level, 61.6dB of SNDR for 4.5MHz input signal. Under 1.8-V supply, the power consumption of the proposed ADC is 68.5-mW. The measured ADC performances achieve -40 dB of Noise Level, 24.8 dB of SNDR for 10MHz input signal. The chip area including I/O pads is 2.52 mm2.