Abstract
Clock and data recovery circuits (CDR) find wide application in digital communication systems. This thesis describes an analog PLL-based clock and data recovery circuit in a 0.35um digital CMOS technology and discusses each building block of phase lock loop circuits in detail. The CDR we proposed operates at 1.25Gb/s which meets SONET OC-24 standard. To achieve a high speed with low power consumption, a 1.25GHz two-stage ring oscillator is introduced; it uses a fully differential architecture to reject noises from supply. A high speed sample-and-hold phase detector whose output pulsewidth is linearly proportional to the input phase difference is also depicted. Also an analog D flip-flop is described here as the decision circuit to regenerate data streams. The circuit is designed with fully differential architecture and employs a low phase noise VCO to reduce jitter. The simulated jitter generation is 45 ps peak-to-peak for a PRBS sequence of length 223-1. The core circuit dissipates a total power of 52.64mW from a 3.3V supply and occupies an area of 0.75 × 0.6 mm2.