Abstract
To scale CMOS field-effect transistors (FETs) well into the sub-20nm region, multi-gate structure, such as, FinFET is adapted as the mainstream technology solution for the suppression of short channel effects. However, epitaxial S/D regions and aggressively scaled channel length lead to enhanced parasitic effect. The serious parasitic effects affect the device performance and limit the further scaling of CMOS technology . In the past decades, several extraction methodologies for characterizing the parasitic resistance from the total device resistance under conduction were proposed. In these conventional methods, constant channel mobility and constant effective channel length under different vertical field are often their basic assumptions. While comes to the generation of FinFET device, most of them then returns inaccurate value due to strong short channel effect and apparent current crowding effect. In this work, multiple characterization methods on a series of test patterns including traditional Kelvin Structures and Cross Bridge Kelvin Structures are discussed and verified experimentally under mature FinFET processing. The new extraction methods become insensitive to constant mobility and Leff assumptions, hence more accurate and consistent results can be obtained, giving a practical overview of parasitic resistance in a FinFET device.