Abstract
This thesis describes a 20MHz, 8-bit resolution CMOS pseudodifferential sample-and-hold circuit with double sampling, which is to be mainly intended for front-end use in analog-to-digital converters. The circuit is composed of an operational amplifier, unit gain buffer, capacitors, MOS transistor switches. The folded-cascode amplifier is used in our design of the operational amplifier. From the simulation, a DC gain of 69.5dB, and a unit gain frequency of 120MHz, are obtained. The sample-and-hold circuit has been designed with a TSMC 0.25 um 1P5M CMOS technology. Total power consumption is 12.0 mW from 2.5V and 3.3V supply, and the chip area measures 831×831 um2.