Abstract
In recent years, the improvement of power electronics and power devices is one of key forces for energy efficient appliances in modern day lives. Continuous cost down and the tradeoff between breakdown voltage and on-resistance have always been major concerns in designing power devices. Most of the power devices in IC require some or substantial changes from generic CMOS process. However, these special processes and/or discrete power devices connected through wire bonding prevent the power circuits to be cost down further.On the other hand, scaled COMS technology creates high surface electric field, which seriously limit its operation voltage. It will be very hard to design HV circuits in advance CMOS technologies due to lack at HV devices. This work presents floating field plate (FFP) design for 28nm high-k metal gate MOS transistors. Floating metal gates are employed to extend the corner electric field at edge of drain junction under the thin core gate dielectric layer. The design of floating field plate on potential profiles and surface electric field distributions are studied by simulation data. Measurement results demonstrated that the floating field plates can effectively raise the gated breakdown voltage to the junction limit without process modifications. This fully logic compatible device does not need the additional masks of and/or wire bonding process for connection, hence, can be extended to various applications such as embedded memories.