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32位元處理器之定點數MFCC演算法的改進與探討
Thesis

32位元處理器之定點數MFCC演算法的改進與探討

陳奕宏
Masters, 國立清華大學, 資訊系統與應用研究所
2005

Abstract

梅爾倒頻譜 離散餘弦轉換 快速傅立葉轉換 對數表 開方根表 調整參數 MFCC DCT FFT Log table Square Root Table Scale Up/Down Parameter
In this thesis, we investigate the possibility of porting the computation of floating-point MFCCs to fixed-point ones. In particular, we focus on the platform of 32-bit fixed-point processors. We have closely checked the scaling factors during each stage of the computation of MFCC by using a data-driven approach. These scaling factors are carefully chosen such that the highest precision is achieved with low probabilities of overflow. Moreover, we have proposed a binary-search-based table lookup such that the required table size is reduced. In summary, the proposed methodology can greatly reduce the memory requirement without degrading recognition rates.

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