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3D IC bumping high performance Multi-source Pick & Place Equipment Development
Thesis

3D IC bumping high performance Multi-source Pick & Place Equipment Development

Tseng, Weu-Yuen
Masters, 國立清華大學, 經營管理碩士在職專班
2015

Abstract

CoWoS 3D IC 封裝技術 New tool purchase spec決策分析 Pick and place WPH改善 CoWoS 3D IC package New tool Purchase spec decision making Pick and place WPH improvement
With the absent of the end of Moore’s Law, all semiconductor foundries are working on another way to break through the physics limitation. All this efforts such as MEMS, Ultra-Low-Power IC, Mixed Signal IC and 3D-IC etc are called “More-than-Moore.” Among More-than-Moore, the most likely solution to extend Moore’s Law is the 3D-IC technology. As a core process of 3D-IC, Pick & Place process (P&P) is getting more and more important and being expected to have more powerful function nowadays. Traditionally in prior art, tool only allows 10 configurations to select and re-arrange different bin codes, but the customer usually have more than 10 configurations on each order. As a result of that, manually revising bin configurations during an order is needed. That causes the automation of equipment to be limited. Another issue is for the next generation 3D-IC based GPU, DRAM and GPU have to do P&P in the same stage in order to cost down. DRAM likely comes from Tape & Reel (T&R) or Film Frame (FF) packages, and GPU comes from film frame package (but with 2 different types.) The above complexity causes P&P process manually, low WPH, high MO risk and high CoO. We developed an all in one die bonder as a solution, it merges T&R, 2 types of film frame process in the same time and it’s automatically, high WPH, no MO risk and lower CoO. Moreover, it supports bin configurations to be controlled by each substrate to solve the 10 configuration limitation and to achieve the real automation.

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