Abstract
The three-dimensional integrated circuit (3D IC) is considered a promising approach that can obtain high data band-width and low power consumption for future electronic systems that require high integration level. One of the popular drivers for 3D IC is the integration of a memory stack and a logic die. Because the yield of a 3D IC is the product of respective yields of the mounted dies, the yields of the memory dies and logic die must be high enough, or the 3D IC will be too expensive to be manufactured. It is generally agreed that the yield of large memories that are manufactured with advanced technologies is lower than the logic die. As a consequence, to obtain a high yield of 3D ICs, efficient test and repair methodologies for memories are necessary. In this thesis, we target the wide-I/O dynamic random access memory (DRAM) and propose two 3D redundancy architectures, i.e., Cubical Redundancy Architectures 1 and 2 (CRA1 and CRA2). In CRA1, spares are associated with each DRAM die as in a conventional 2D architecture. In CRA2, we use a static random access memory (SRAM) on the logic die as spares. We implemented both CRA1 and CRA2, and compared their repair rates as well as area overhead with the traditional redundancy architecture (TRA). Experimental results show that the CRA1 can obtain up to 3% higher stack yield than the TRA with the same area overhead. On the other hand, the CRA2 can obtain the same yield as the CRA1 with 40% less spares, but 1.27% higher area overhead than the CRA1.