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4 ch數位即時監視系統之系統架構: 視訊多工器與反多工器之設計與實作
Thesis

4 ch數位即時監視系統之系統架構: 視訊多工器與反多工器之設計與實作

吳家豪
Masters, 國立清華大學, 電機工程學系
2003

Abstract

監視系統 多工器 反多工器 DVR multiplexer de-multiplexer
In contrast with PC-based Digital Video Recorder (DVR) system in surveillance applications, the standalone DVR has several advantages such as lower cost, more rugged, easier maintenance, and smaller size. Moreover, the multi-channel design can further increase the utilization efficiency of the DVR hardware and meet the various demands of increasing surveillance applications. In this study, our goal is to design a standalone 4-channel DVR system which exhibits the real-time, high video quality (up to 30 fields/sec/channel high-quality NTSC signal) capabilities. In addition, the system should allow for easy extension to accommodate intelligent surveillance functions, such as intelligent search, pattern recognition, etc. To meet these goals, we first propose the system architecture of a 4-channel DVR which uses a DSP chip (TI’s TMS320C6711) as its central unit providing the flexibility of adding more functionalities to the DVR, two wavelet-based video chips (ADV612) as the compression/decompression engine to achieve high image quality and compression efficiency, and three FPGA chips (ALTERA EP1C3T144C8) for interface logic and video signal multiplexer/de-multiplexer. Then we designed a digital video multiplexer (MUX) circuit to multiplex the incoming 4-channel input digital video signals together to be compressed by the ADV612 compression chip. During playback, a video de-multiplexer (DEMUX) circuit is also designed to generate 4 channel full video signals from the decompressed output video signal of the ADV612. Considering the asynchronous characteristics of the incoming 4 channel video signals, at least a video field buffer is needed in the MUX/DEMUX design, which is best implemented by SDRAM due to its capacity/cost/speed requirements. Therefore, an SDRAM controller circuit is also designed on the same FPGA. A prototype 4-ch DVR system board has been designed and implemented which successfully illustrated the validity and functionality of our MUX, DEMUX design. Furthermore, the use of FPGA in our design could easily allow for many extra functions to be implemented into the system, such as raw image extraction for intelligent DVR like pattern recognition, on-screen display (OSD), information or audio insertion into NTSC blanking, as well as freeze, zoom, quadrant and PIP functions, etc.

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