Abstract
In HV process, manufacturing adjustable pinch-off voltage and saturation current JFET without adding any additional mask is beneficial to integrate other device on a single chip. In this thesis, we use process and electric simulation tools to analyze the 0.5 µm HV process JFET characteristic by varying different layout. Furthermore, we design a pinch-off voltage adjustable JFET. The simulation tools are also utilized to design a saturation current JFET. Through practical tape-out, N channel JFET are successfully integrated in 0.5 µm HV process, which provides more choice of devices for circuit designer. Designers can also make use of the merit of the proposed JFET to integrate on a single chip and promote circuit performance.