Abstract
A design of the low jitter phase-locked loop based upon self-biased and wideband techniques are presented. Avoiding the need of external biasing, self-biasing generates all the internal bias currents and voltages and has fixed bandwidth to operate frequency ratio independent of process, voltage and temperature. This property minimizes jitter, and to further reduce the jitter, the loop bandwidth should be set as wide as possible. Simulated in 0.35um CMOS with supply of 3.3V, the synthesizer can achieve peak to peak jitter 53.9ps and RMS jitter 9.216ps at 450MHz operating frequency.