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5.2 GHz CMOS射頻前端電路設計
Thesis

5.2 GHz CMOS射頻前端電路設計

蘇炳誠
Masters, National Tsing Hua University
2003

Abstract

低雜訊放大器壓控震盪器混頻器RFCMOS射頻前端電路
In this thesis, we design a radio-frequency front-end circuit block base on TSMC 0.18um RF CMOS process model. The circuit includes low-noise amplifier (LNA), voltage-controlled oscillator (VCO) and mixer. The LNA frame is the common-source with inductive degeneration LNA, VCO is complementary cross-coupled pair structure, and mixer structure is the active Gilbert cell. The output specifications of the designed circuit blocks follow the IEEE 802.11a WLAN specifications. Some specifications except IEEE 802.11a WLAN specifications reference to other papers or researches. The input RF frequency of our designed blocks is 5.2 GHz, LO output frequency is 5.0 GHz, and IF output frequency is 200 MHz. We use ADS RF software to simulate the circuit, and use ASITIC inductor model to design inductors that are not involved in TSMC model. Considering about the process variation, we simulate circuit with corner cases supported by TSMC model to verify our design. The independent unit circuit important output results are listed as the following : The LNA S11 is -15.87 dB, NF is 2.29dB, mixer IIP3 is -0.05dB, conversion gain is -0.23dB, and the VCO phase noise is -109.4 dB at 1MHz offset frequency. In order to avoid the substrate feed-through and loading effect, we insert a buffer circuit between VCO and mixer to increase the port to port isolation. Finally, we merge all independent units to form the core circuit blocks that we wanted. The block circuit output results are: S11 is-13.75 dB, conversion gain is 19.93dB, NF (50Ω) is 4.69 dB, IIP3 is 16.94 dB, and of the entire circuit power consumption is 46.46mW. The final output result is conformed to IEEE 802.11a WLAN specification at all corner cases.

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