Abstract
This thesis presents a 0.5V 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) using adaptive time-domain comparator with noise optimization. The proposed ADC operates at low supply voltage 0.5V to save power consumption. The proposed adaptive time-domain comparator can adjust comparator noise performance with input value. While input signal is large, the input-referred noise of comparator decreases and the power consumption increases. While input signal is small, the input-referred noise of comparator increases and power consumption decreases, which can save more power during 12bit conversion. The prototype was fabricated in 90nm 1P9M CMOS technology with a core area of 156.96×693.63μm2. At 0.5V supply voltage and 100kS/s sampling rate, the ADC achieves SNDR from 66.26dB corresponding ENOB from 10.71bit at Nyquist-frequency input and consumes 0.81μW power, resulting in a figure of merit (FoM) from 4.82 fJ/conversion-step.