Abstract
ABSTRACT This thesis proposes a 10-bit column-parallel successive approximation (SAR) analogue-to-digital converter (ADC) used for sensor array applications. A multiple segmented charge redistribution capacitive digital-to-analog converter (MS-C-DAC) is employed to reduce the area and power consumption. To solve the inherent mismatch issue of segmented DAC, a new digital calibration method is proposed, which improves SNDR from 51.79 dB to 57.63 dB. The prototype experimental chip is fabricated by 0.18um CMOS technology. The prototype ADC operates with 1V supply and 4MS/s sampling rate. The measured effective number of bits (ENOB) at near Nyquist frequency is 9.28-bit. The differential non-linearity is reduced from +0.52 / -1 LSB to +0.62 / -0.65 LSB, and the integrated non-linearity is improved from +3.2 / -3.1 LSB to +0.64 / -0.48. The total power consumption of 53.5uW is achieved, and the resultant figure of merit (FoM) is 21.5fJ/Conversion-step.