Abstract
This thesis presents an ultra-low voltage and power-efficient 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC) for Internet of Things (IoT). The proposed ADC operates at ultra-low supply voltage from 0.35V to 0.5V to save power consumption. This architecture reuses a comparator as a voltage-to-time converter and implements a time-domain quantizer. The comparator converts voltage difference of input signal sampled on DACs to MSB result and the corresponding comparison time simultaneously, and then time-domain quantizer detects the input range. An input-range-adaptive (IRA) switching method is proposed to significantly reduce the average switching power of capacitive-DAC (CDAC) and keep common-mode voltage constant. The prototype was fabricated in 90nm 1P9M CMOS technology with a core area of 390×97μm2. At 0.35V-to-0.5V supply voltage and 300kS/s-to-2MS/s sampling rate, the ADC achieves SNDR from 55.5dB to 56.3dB corresponding ENOB from 8.92bit to 9.06bit at Nyquist-frequency input and consumes power from 0.3μW to 2.5μW, resulting in a figure of merit (FoM) from 1.94 fJ/conversion-step to 2.32fJ/conversion-step.