Abstract
This thesis presents a 10-bit low-voltage and high power efficiency successive approximation register (SAR) analog-to- digital converter (ADC) for wireless sensor networks and biomedical devices applications. The proposed ADC operates at ultra-low supply voltage from 0.4V to 0.7V to save power consumption. Several techniques are utilized to improve the power efficiency of the ADC in low voltage operation. The charge-average switching (CAS) technique is proposed to reduce digital-to-analog converter (DAC) switching energy and relax the driving requirement of switch buffer at high speed conversion phase. Without common-mode voltage variation and extra reference generator, improves the linearity and power efficiency at low voltage operation. A self-time variable delay controller optimizes the settling time of DAC improving the conversion speed. The prototype was fabricated using 90nm 1P9M CMOS technology and core area is only 110×380μm2. At 0.4-to-0.7V supply and 0.5-to-4MS/s sampling rate, the ADC achieves SNDR from 54.3 to 56.3dB corresponding ENOB from 8.73 to 9.06 at Nyquist-rate input and consumes 0.5-to-11μW power consumption, resulting in a figure of merit (FOM) from 2.4 to 5.2fJ/conversion-step.