Abstract
As wireless communication systems develop rapidly, the transceiver circuit design has been surveyed for years. In the RF front-end system, the essential component, frequency synthesizer, still needs to be further improved especially in the aspects of faster switching speed, higher operation frequency, and lower phase noise. In this integer-based architecture, there exists laborious trade-off between the frequency resolution and the switching speed. It cannot achieve fine frequency resolution and fast switching speed at the same time. Because the bandwidth of the loop has to be proportional to the frequency Fref, the higher the frequency resolution is, the narrower the bandwidth will be. As a result, a trade-off is inevitable between frequency resolution and loop bandwidth.Alternatively, the fractional-N frequency synthesizer is used to improve the trade-off; namely, to provide higher loop bandwidth and faster switching speed simultaneously. As compared with the conventional technique, the operating speed of frequency synthesizer is advanced up to giga hertz in prevailing CMOS technology. Taking the advantage of today’s advanced CMOS technology, this thesis will demonstrate how to design a high-performance frequency synthesizer by using innovative techniques. The design of the 1.5V 2.4GHz frequency synthesizer in this thesis aims at the 2.4 ~2.472 GHz ISM band and is implemented in TSMC 0.25μm 1P5M CMOS technology. In order to minimize the phase noise, two methods, namely visualization of design constraints and three-dimensional phase noise analysis diagram, are suggested to determine the optimum bias condition. Moreover, a phase noise prediction model, which is suitable for both hand calculation and computer analysis, is presented. As a result, the design process is shown to be more systematic and accurate.