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A 2.4-GHz Fully Digital-Controlled Synthesizer-based Binary Frequency-Shift Keying Transmitter
Thesis

A 2.4-GHz Fully Digital-Controlled Synthesizer-based Binary Frequency-Shift Keying Transmitter

Chiang, Ping-Chung
Masters, 國立清華大學, 電機工程學系
2009

Abstract

射頻發射器 二進制頻移鍵控 頻率合成器 數位濾波器 鎖相迴路 逐次漸進式暫存器 RF Transmitter Binary Frequency-Shift Keying Synthesizer Digital filter Phase-locked loop Successive approximation register
This thesis presents a fully digital-controlled binary frequency-shift keying (BFSK) RF transmitter for 2.4-GHz Industrial, Science, and Medical band (ISM-band) applications. Compared with analog-controlled transmitters, this one is much less to the process variation and noise interference. The transmitter control scheme is realized by a successive approximation register (SAR) loop and a digital phase control loop. The former loop is used to calibrate the initial output frequency, and the latter is used to compensate the output frequency drift. By incorporating both loops, fast and accurate data transmission can be achieved. The key block of the transmitter is a digitally controlled oscillator (DCO). Its varactor is composed of two switched-capacitor arrays. Two extra capacitors are added for reduction of the capacitance variation. A gated ripple counter is used to estimate the DCO frequency for the SAR and phase control loops. Before data transmission, the SAR loop generates and stores the oscillation tuning words (OTW) of DCO for logic-0 and 1. During data transmission, the phase control loop is enabled to maintain the DCO frequency close to the desired one. This design is implemented in TSMC 0.18-μm 1P6M CMOS process and its chip area is 1 □× 1 mm2. According to measurement results, the oscillation frequency range is 2.327 ~ 2.405 GHz, and the phase noise is below -79.8 dBc/Hz at 1 MHz offset. For 250-kbps data transmission, the frequency error is less than 500 kHz. The total power consumption is around 17.6 mW under 1.8 V power supply.

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