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A 3D Product Code for Enhancing Memory Reliability
Thesis

A 3D Product Code for Enhancing Memory Reliability

Wu, Shu-yu
Masters, 國立清華大學, 電機工程學系
2011

Abstract

乘積碼 記憶體 三維晶片 可靠度 product code memory 3D ic reliability RAM
In this thesis we modify the traditional product code to propose a 3D product code for enhancing memory reliability. The correction ability of the 3D product code is better than traditional product code because it is a double error correction (DEC) code rather than a single error correction (SEC) code which the traditional product code is. The use of parity bits in the 3D product code is more than in traditional product code. We discuss the way of encoding and decoding, and how to correct single error and double errors. We also design the hardware of the encoder and decoder. In order to estimate the tradeoff between the parity cost and MTTF benefit, we proposed an index called “MTTF to overhead.” We find out although 3D product code needs more area (an additional layer of parity bits) but gains higher reliability and MTTF than the traditional product code by the index. Finally we find out there is opportunity to correct triple errors without increasing additional parity bits by the 3D product code, so how to design a triple error correction (TEC) 3D product code is a worthy way to do.

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