Abstract
More and more SRAMs are used in high-end SoC, because they have many advantages such as high speed and process compatibility. However, SRAMs will be a bottleneck for decreasing power consumption in low power system such as mobile consumer electronics. Hence, if SRAMs can operate at lower voltage, its power consumption will be decreased. However, a conventional 6T SRAM cell suffer from various variations due to voltage and technology scaling, the probability of access failure will be much increased. The data of SRAM cell suffer from leakage currents at low voltage and needs a high data retention voltage. For access operation, the data of selected cell and unselected cells suffers from read and half-selected disturbance, respectively, due to they share same word line in a row. Hence, novel cell structure and peripheral circuits are used to improve the stability at low voltage especially. Some published works such as 8T~10T SRAM cells are proposed, but these decrease memory density due to larger cell area. Actually, it always cannot be accepted by industries because of cost considering. Hence, we propose a novel 7T SRAM cell. We add 1T decoupled-read port in 6T cell, this eliminates read-disturb and makes the read SNM of 7T cell is similar to hold SNM. Hence, we have more sizing space to achieve larger write margin. Boosted read bit line (RBL) scheme is used to increase sensing margin for sense amplifier, and it decreases clamping current also. For unselected rows, VDD-driven read word line scheme is used to suppress the leakage of RBL. For write operation, read-first and write-back scheme is used for unselected cells to prevent write half-selected-disturb issue. The cell size of 7T cell is just 1.1 times that of conventional 6T cell. Finally, 32kb 7T SRAM test chips are fabricated in 65nm CMOS technology. In measurement results, this work can operate at 0.34-V~1-V, and the VDDmin of this work is 370-mV at 23-MHz. If the boosted RBL scheme is used, the VDDmin can lower to 340-mV at 22-MHz.