Abstract
In this thesis, we present a built-in self-test methodology for testing the network-on-chip (NoC). This methodology uses transition fault model. And the NoC model is a 2-dimensional mesh which is TG2 benchmark. The proposed method is using BIST to generate test patterns to test processing element. And utilize inter-switch to send packets to test other processing element in NoC communication infrastructure. And this BIST design is sharing test pattern generator (TPG) and multiple-input signature register (MISR) for all processing elements. Every processing element has a test controller, all of these test controller chain together, and connect to the central test controller. Control signals sending to which processing element and the action of processing element will be decided by the central test controller, such as assign which router to test circuit. Our propose target is to decrease area overhead and improve performance for this BIST architecture.