Abstract
Locking the frequency and phase between external and internal clocks, the phase-locked loops (PLLs) are fundamental elements in microelectronic systems. Traditionally, the analog PLL is designed for this task and the problem is that digital circuits such as CPU would affect the PLL’s performance in embedded system. To solve this problem, the all-digital phase-locked loop (ADPLL) is introduced by using full digital technology to obtain the advantages of wide locking frequency range, less phase error, process independence and good stability. The Design for-testing (DFT) and Built-in Self-test (BIST) have been appeared to test the digital electronic circuits recently. How to design the BIST structure of the embedded ADPLL is the motivation of doing this work. The ADPLL consists of phase detector (PD), frequency comparator (FC), phase gain (PG), frequency gain (FG), adder/subtract, anchor register, Digital Control Oscillator (DCO) and its register, and control block. Those are all made of digital circuit, but some special characteristics discussed below would strongly influence the test method. According to the simulations by CAD tools SPICE and Verilog, the special characteristics are as follows. 1. The ADPLL had analog signal properties (frequency and phase). 2. Temperature is impacted on DCO. 3. The fault tolerance characteristic in the ADPLL. In this thesis, a novel BIST design for testing the ADPLL is proposed with area penalty of about 10% and over 95% fault coverage in the operation range of 280 MHz to 500MHz by applying a 0.6 □m cell library. The modified ADPLL requires 1723 gates including 166 gates of BIST scheme. The fault model includes behavior fault in single functional block, and multiple stuck-at faults at circuitry block.