A Built-In Self-Test Scheme Covering Hard-to-Detect Defects in FinFET-Based SRAM

Thesis

Chen, Meng-Chi

Masters, 國立清華大學, 電機工程學系所

2017

Abstract

內建自我測試

缺陷模型

可測試性設計

動態錯誤

錯誤模型

鰭式場效電晶體

記憶體測試

靜態隨機存取記憶體

Built-in self test

Defect modeling

Design for testability

Dynamic fault

Fault modeling

FinFET

Memory testing

SRAM

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Title: A Built-In Self-Test Scheme Covering Hard-to-Detect Defects in FinFET-Based SRAM
Translated title: A Built-In Self-Test Scheme Covering Hard-to-Detect Defects in FinFET-Based SRAM
Creators: Chen, Meng-Chi
Contributors: Wu, Cheng-Wen (Advisor)
Awarding Institution: 國立清華大學, 電機工程學系所; Masters
Theses and Dissertations: Masters, 國立清華大學, 電機工程學系所
Language: English
Resource Type: Thesis
Date published: 2018