A Cell-Based Compiler for Process Resilient Fractional-N All-Digital PLLs

Thesis

Lee, Cheng-En

Masters, 國立清華大學, 電機工程學系所

2016

Abstract

全數位式鎖相迴路

非整數型頻率合成器

多模數除頻器

數位控制震盪器

全數位式鎖相迴路編譯器

All-Digital Phase-Locked-Loop (ADPLL)

Fractional-N Frequency Synthesizer

Multi-Modulus Frequency Divider

DCO

ADPLL Compiler

abstract hide

1 Record Views

Title: A Cell-Based Compiler for Process Resilient Fractional-N All-Digital PLLs
Translated title: A Cell-Based Compiler for Process Resilient Fractional-N All-Digital PLLs
Creators: Lee, Cheng-En
Contributors: Huang, Shi-Yu (Advisor)
Awarding Institution: 國立清華大學, 電機工程學系所; Masters
Theses and Dissertations: Masters, 國立清華大學, 電機工程學系所
Language: English
Resource Type: Thesis
Date published: 2017