Abstract
Voltage scaling has been shown to be an effective method to reduce power consumption. However, one of the penalties of this method is the reduction of circuit performance. In this thesis, we study various low power circuits operating in sub-threshold region and propose a body biasing socket circuit for performance and standby power optimization. The VTMOS circuit can give a proper body bias to the circuit with an external circuit, but it consumes more power to charge and discharge the body capacitance. Without the external biasing circuit, the circuit with body biasing socket uses the body sharing method to charge the NMOS body capacitance with PMOS body capacitance. It doesn’t bias the circuit by charging the body capacitance with external circuit and can save the power. This circuit, when turns on, shares the body charges of the NMOS and PMOS transistors and thus improves the transistor performance. For a simple 4-bit Ripple Carry Adder, we find the performance improved 26% as compared to the standard CMOS circuit. When the socket is turned off, the standby power is only 2.3% larger than the standard CMOS adder. In contrast the DTMOS (Dynamic Threshold MOS transistor) circuit has lower speed and with 500X larger standby power compared to the standard CMOS circuit. In addition, the area increases with the adder circuit is also much smaller with the body biasing socket method. In this thesis, in order to get accurate performance and standby power estimation, the transistor body terminals and the N-well, P-well parasitics are also carefully modeled. We believe with these added models, the comparisons are more meaningful.