Abstract
This thesis presents an efficient collaborated stochastic low-density parity-check (LDPC) decoder, where a bit-flipping (BF) based collaborative decoder is used to achieve less decoding cycles without degradation in bit-error-rate (BER) performance. A node-wise probability tracer is adapted at each variable node (VN) in order to achieve a BER performance comparable to the normalized min-sum algorithm, where the check-to-variable (C2V) messages rather than the variable-to-check (V2C) messages adopted in the previous stochastic decoders are used as inputs. The complexity of VN units is greatly reduced by sharing common units used in the generation of V2C messages and the probability tracer. The C2V-based probability tracer enables the design of a decoder with short critical path. The proposed methods are demonstrated by implementing a (2048, 1723) decoder. Fabricated in a 90nm process, the decoder integrates 1460K logic gates in 4.12 mm^2 and achieves a throughput of 39.3 Gbps at a clock of 749 MHz. To the best of our knowledge, the proposed decoder achieves the best BER performance and normalized throughput-to-area ratio among the stochastic decoders reported in the open literatures.