Abstract
This thesis proposes a Critical-Section-Level timing synchronization approach for deterministic Multi-Core Instruction-Set Simulation (MCISS). By synchronizing at each lock access instead of every shared-variable access and with a simple lock usage status managing scheme, our approach significantly improves simulation performance while having all critical sections executed in a deterministic order. Experiments show that our approach performs in average 295% faster than the shared-variable synchronization approach and the approach can effectively facilitate system-level software/hardware co-simulation.