Abstract
In today’s SOC chip, non-volatile memory plays an important role to store the data from other peripheral unit and can read out repeatable. With the technology shrink, the cell array in same area is larger and larger. However, the cell current is also decreased not only NOR type flash but also NAND type flash or OTP and difficult to read. With the nanometer technology, the transistor threshold voltage mismatch gets more pronounced and making the sensing failure easily. To solve this problem, we propose a new current mode sense amplifier with offset suppress scheme. In this design, we sample the input current and amplify the difference without regard the threshold voltage variation. Furthermore, we use symmetric array to reduce mismatch between cell side and reference side and use average technique to reduce the variation on reference current due to PVT variation. We apply our design in 90nm CMOS technology within 512Kb OTP. The experiment result shows that, the minimum cell current can be read in 100nA reference current condition and power supply 1.2V is 140nA.