Abstract
In this thesis, a digital control adaptive PLL with a BCU (Bandwidth Control Unit) and jitter measurement BIST is proposed to reduce the locking time as well as measure the long-term jitter of the PLL. The locking status is detected and digitized by the measurement BIST, which sends signal to the BCU and controls the loop bandwidth. Thus the loop bandwidth could automatically switch to two times of the normal bandwidth when it's out of lock and the locking time could be reduced 50% ideally according to the mathematic model. The normal loop bandwidth is 3MHz in steady state and the wider loop bandwidth is 6MHz when out of lock. The PLL is implemented under TSMC 0.18μm CMOS process and the supply voltage is 1.8V. The input frequency is 50MHz and the output frequency is 1.6GHz. The post-simulation result shows that the locking time is 0.89μs in the proposed digital control adaptive PLL and 1.37μs in conventional PLL with 3MHz fixed loop bandwidth.