Abstract
In many circuits, PLL “Phase Locked Loops” plays an important role in an output high speed clock to follow the slow input clock. Examples of application that uses PLL include clock and data recovery, delay locked loops, clock synthesis, and synchronization. In this thesis, we propose a dual mode PLL, which functions as sampling a DC-balanced or error detection 8B/10B data in the time domain of OFDM system to reduce PAPR. Based on the architecture, the jitter performance of PLL is getting more and more important, as communication system request higher data rate. The thesis proposes the complete flow chart which establishes the PLL block. It estimates LC-VCO phase noise in frequency domain and Dual Mode PLL jitters in time domain. Moreover, the proposed LC-VCO has very low phase noise and can be used to work at dual speed. The PLL have been designed and fabricated in a 0.18um TSMC CMOS Mixed Signal technology .The chip area is 1.2mm * 1.2mm. The VCO operation frequency is 1280MHz and 1600MHz. The power consumption is 34mW and supply voltage is 1.8V. The performance of peak to peak jitter is 2.3ps at 1.28GHz and 2.5ps at 1.6GHz.