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A Dynamic Dispatching Approach for Semiconductor Wafer Test
Thesis

A Dynamic Dispatching Approach for Semiconductor Wafer Test

Lieh-Chang Tai
Masters, 國立清華大學, 工業工程與工程管理學系
2001

Abstract

晶圓針測 晶片測試 動態派工 CP (Circuit Probing) Dynamic dispatching Wafer probing Wafer test
With the development of semiconductor advanced technologies (0.15um à 0.13um à 90nm) is rising and competing drastically, the wafer test plays a more significantly important role in providing the promptest yield feedback for quick process improvement. Nevertheless, the shop floor of wafer test is getting even complicated than before due to the increasing change over rate, non-linear wafer arrival and urgent orders preemption behavior. Furthermore, the foundry wafer test is a heterogeneous production with different products of cycle time and non-identical testers in large variance. The shop floor condition including WIP pool, tester status and work order priority keeps changing all the time. In order to operate such kind of production line to simultaneously fulfill the multiple objectives such like maximum CLIP (confirmed line item performance) for normal lots, 100% CLIP for urgent lots, minimum change-over rate and shortest cycle time, a reactive dispatching approach, which is expected to perform a real-time solution no matter how/what the shop floor would change dynamically, is proposed. The dynamic approach is mainly triggered by two kinds of major events, one is when an urgent lot come in, and the other is when a tester is idle. In addition, through a two-phase dispatching algorithm, lot ranking and lot assignment methods, prioritized WIP lots and an appropriate lot assignment are suggested. The experimental results reveal that the better performance measure is obtained under the entire consideration of multiple objectives, which are the wafer test operations desire to achieve.

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