Abstract
In VLIW processor design, clustered architecture becomes a popular solution for better hardware efficiency. But the inter-cluster communication (ICC) will cause the execution cycles overhead. In this paper, we propose two kind of architecture to reduce the ICC overhead. One is shared cluster register file (SCRF) and the other is wired shared cluster register file (WSCRF). SCRF is software-based architecture and doesn’t mention about the wire delay parameter in real-time environment. We use WSCRF to prove that SCRF is available in hardware area. The SCRF architecture is a hybrid register file (RF) organization composed of shared RF (SRF) and clustered RFs (CRFs). By putting the frequently used variables that need ICCs on SRF, we can reduce the number of data communication of clusters and thus reduce the ICC overhead. The SCRF register allocation algorithm exploits this architecture feature to perform optimization on ICC reduction and spill codes balancing. The SCRF register allocation algorithm is a heuristic based on graph coloring. To evaluate the performance of the proposed architecture and the SCRF register allocation algorithm, the frequently used two-cluster architecture with and without the SRF scheme are simulated on Trimaran, a compiler framework. The WSCRF architecture is used to prove the viability and complete the deficiency of SCRF. We solve the issue of wire delay in SCRF through experiment. A set of multimedia programs from mediabench is used as the benchmarks. The simulation results show that the performance of the SCRF architecture is better than that of the clustered RF architecture for all test programs in all measured metrics. In the SCRF architecture with macro registers defined in the SRF, the execution cycles, the ICC overhead, the spill codes overhead, and the code density can get 11.6%, 55.6%, 52.7%, and 18.2% reduction in average, respectively. Same multimedia programs from mediabench are used as the benchmarks for WSCRF. The simulation results show that the performance of WSCRF architecture is closed to the reality. In terms of the execution cycles, the ICC overhead, the spill codes overhead, and the code density. We set the wire delay as 1, 2 and 3. In cycle count=1, we get 6.5%, 6.8%, 4.05%, 9.2% reduction, respectively. In cycle count=2, we get 4.5%, 3.6%, 3.1%, 9.1% reduction, respectively. In cycle count=3, we get 2.5%, -0.6%, 2.4%, 9.1% reduction, respectively.