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A Fast-Lock Adaptive PLL using Digital Bandwidth Control Unit with Hybrid Division Mode and Current Intension
Thesis

A Fast-Lock Adaptive PLL using Digital Bandwidth Control Unit with Hybrid Division Mode and Current Intension

Li, Ming-Syuan
Masters, 國立清華大學, 電機工程學系
2008

Abstract

適應性 鎖相迴路 adaptive PLL phase-locked loop
A high bandwidth ratio adaptive PLL with Digital BCU(Bandwidth Control Unit) is proposed in this thesis. There are two ways to enhance the bandwidth ration. The first method is to change the bandwidth by 4-fold increase in the charge pump current. The second method is to change the bandwidth by 16-fold reduction in the multiple of the frequency divider. The total bandwidth ratio is eight, two times from the former and four times from the latter. If the loop is out of lock, the system operates at the fastest speed of 3.2MHz. Then the bandwidth switches to 1.6MHz by current adaptive method when the loop is half-locked. Final, the loop is locked and the bandwidth of the system switches to 400KHz by divider method. The locking time of the proposed PLL is 2.6us as well as the locking time of the conventional PLL is 16.1us in the simulation result. The total time improvement is 83.85%.

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