Abstract
Static timing analysis has always been indispensable in integrated circuit design. In order to consider design and electrical complexities (e.g., crosstalk coupling, voltage drops) as well as manufacturing and environmental variations, timing analysis is typically done using an “early-late” split. The early-late split timing analysis enables timers to effectively account for any within-chip variation effects. However, this dual-mode analysis may introduce unnecessary pessimism, which can lead to an over conservative design. Thus, common path pessimism removal (CPPR) is introduced to eliminate this pessimism during timing analysis. A naive approach would require the analysis of all paths in the design. For today’s designs with millions of gates, enumerating all paths is impractical. In this thesis, we propose a new approach to effectively prune the redundant paths and develop a multithreaded timing analysis tool called MTimer for fast and accurate CPPR. The results show that our timer can achieve 3.53X speedup comparing with the winner of the TAU 2014 contest and maintain 100% accuracy on removing common path pessimism during timing analysis.